Integrated circuit semiconductor memories must, of necessity, operate with a high degree of reliability in order to be used in computer related applications. The production of errors on even infrequent occasions can cause serious problems in computer controlled operations and data processing. The nature of MOSFET (metal-oxide-semiconductor field-effect transistor) memories is such that error conditions are not always consistent but frequently occur only under unique circumstances. In mass produced memory circuits, certain ones of the memories will have greater resistance to error conditions while others will be more prone to the generation of errors.
Testing schemes have therefore been developed to determine the reliability of such semiconductor memory devices under normal and subnormal operating conditions. In semiconductor memory testing, memory cells are exercised in a number of ways in order to determine if weak or misfunctioning cells exist. The identification of these weak cells or marginally acceptable cells results in rejection of the entire semiconductor memory or substitution for these unacceptable cells using redundant elements.
A common method for testing semiconductor memories is to apply a reduced supply voltage to the semiconductor memory which causes an abnormal reduction in operating margin, thereby accentuating some weaknesses and potential failures. Margin testing has heretofore been accomplished with an adjustable supply voltage to measure the operating margins of stored cell voltages for a memory circuit. This testing permits sorting of circuits according to margin levels. With the possibility of such sorting, purchasers of memory products can select the high margin circuits and reject others even though other circuits meet manufacturing specifications. The rejected low margin circuits may be returned to the manufacturer even though they are functional. This practice causes an economic loss to the manufacturer and eventually increases the cost of such memory circuits. Margin testing therefore plays an important test function in the manufacture of semiconductor memory circuits.
Previously developed margin testing techniques in which reduced power supply voltages are supplied to the entire semiconductor memory do not adequately test the memory cell array to determine marginally operating cells. Use of a reduced power supply voltage tests the entire array interface circuitry including the sense amplifiers, input and output buffers, chip select buffer, data input and write enable circuitry. This circuitry is utilized to read and write the memory cells.
In typical margin testing, the supply voltage for the entire semiconductor device would be lowered until the device fails. The failure could occur in either the memory array or in the peripheral interface circuitry. If the peripheral circuitry fails at a higher supply voltage than the memory cells, then the memory cells cannot be tested for margins below that supply voltage. For example, if the semiconductor device is rated to operate between, for example, 4.5 volts and 5.5 volts, devices that only work down to 4.0 volts, for example, would be rejected. However, even if a semiconductor device did not fail during a margin test down to the minimum acceptable voltage level, it is still possible for a weak cell to exist in the semiconductor memory array that does not cause a complete failure of the semiconductor memory. In the above example, it is possible that a weak cell exists but which cannot be detected until its supply is reduced to, for example, 3.0 volts. If the peripheral circuits fail at a higher supply voltage than 3.0 volts, for example, 3.5 volts, then the marginal nature of the weak cell at 3.0 volts cannot be detected, yet the part is a "good" part since it passes the margin test down to 4.0 volts. Therefore, marginally reliable cells may go unidentified because the failure of a memory device could be due to loss of a margin in the peripheral circuits without the opportunity to sufficiently stress the memory cells themselves.
A need has thus arisen for a margin test circuit which isolates the semiconductor memory cells for margin testing without affecting the operation of the peripheral circuits which read or write the memory cell being tested. Such a margin test circuit allows the determination of potentially unreliable cells that may normally pass pattern testing and overall semiconductor device margin testing in which the supply voltage for the entire part is reduced.